The invention relates to an electronic computer memory system having at least two intermediate memory levels between a central processing unit and a main or other memory level. In such a system, the intermediate memory levels generally increase in speed and unit cost, but decrease in size in direct relation to their proximity to the central processing unit. During program execution, data and instructions are exchanged between memory levels (a) to update memory levels farther from the central processing unit to reflect changes in data in memory levels closer to the central processing unit, and (b) to transfer data and instructions from memory levels farther from the central processing unit to memory levels closer to the central processing unit as necessary to continue the program execution.
The overall performance of an electronic computer memory system is related to the speed of each level of the memory hierarchy and to the time required for data to be transferred between the levels of the memory hierarchy when information required for program execution is not found in the memory level closest to the central processing unit. The time required to transfer data between memory levels is proportional to the amount of data to be transferred (for example, the cache line size), the access time of the memory level where the required data resides, and the width of the path between the memory levels in the hierarchy. Computer memory system performance also depends on the availability and number of ports between the memory levels, the processor, and the main memory, and the size of each memory level.